Accepted Papers to be Published

Journal Paper:

1. Liang-Chi Chen, Xing-Yu Chen, Chien-Chung Ho, Chun-Le Yeh, Da-Wei Chang, and Yu-Ming Chang, "Compute-Efficient Content-Defined Chunking for Deduplication on a Real Processing-in-Memory System," accepted and to appear in IEEE Transactions on Computers (TC), 2026.
2. Chiang Kun-Chi, Chih-Yi Lyu, Liang-Chi Chen, Yu-Ming Chang, Chien-Chung Ho, and Wei-Kuan Shih, “HFLSM: A Hybrid Flattened LSM-tree for Write-Efficient Key-Value Stores," accepted and to appear in IEEE Embedded Systems Letters (ESL), 2026.
3. Ying-Sheng Huang, Chia-Chou Chuang, Chien-Chung Ho, Pei-Yin Chen, "CRC-Based Error Detection Mechanism for Multiplicative Inverse in Redundant Basis S-Box," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 2, pp. 746-750, Feb. 2026.
4. Liang-Chi Chen, Chien-Chung Ho, and Yuan-Hao Chang, "Accelerating RNA-Seq Quantification on a Real Processing-in-Memory System," IEEE Transactions on Computers (TC), vol. 74, no. 7, pp. 2334-2347, July 2025.
5. Jalil Boukhobza, Pierre Oliver, Wen Sheng Lim, Liang-Chi Chen, Yun-Shan Hsieh, Shin-Ting Wu, Chien-Chung Ho, Po-Chun Huang, and Yuan-Hao Chang, "A Survey on Flash-Memory Storage Systems: A Host-Side Perspective," ACM Transactions on Storage (TOS), 21(3), 1-59, August 2025.
6. Kun-Chi Chiang, Yung-Chun Li, Wei-Chen Wang, Wei-Kuan Shih, Chien-Chung Ho, ”Enhancing Data Integrity with Efficient Retention-Refilling Programming Schemes,” ACM SIGAPP Applied Computing Review (ACR), vol.24, no. 3, pp. 37-50, Oct. 2024.
7. Yu-Pang Wang, Wei-Chen Wang, Yuan-Hao Chang, Chieh-Lin Tsai, Tei-Wei Kuo, Chun-Feng Wu, Chien-Chung Ho, and Han-Wen Hu, "TCAM-GNN: A TCAM-based Data Processing Strategy for GNN over Sparse Graphs," IEEE Transactions on Emerging Topics in Computing (TETC), vol. 12, no. 3, pp. 891-904, July. 2024.
8. Shin-Ting Wu, Liang-Chi Chen, Po-Chun Huang, Yuan-Hao Chang, Chien-Chung Ho, and Wei-Kuan Shih, "WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories," ACM Transactions on Embedded Computing Systems (TECS), vol. 22, no. 5s, pp. 119:1-119:26, Sep. 2023. (Integrated with ACM/IEEE CODES+ISSS'23)
9. Wei-Chen Wang, Chien-Chung Ho, Yung-Chun Li, Liang-Chi Chen, and Yu-Ming Chang, "Reaping Both Latency and Reliability Benefits with Elaborate Sanitization Design for 3D TLC NAND Flash," IEEE Transactions on Computers (TC), vol. 72, issue 11, Nov 2023.
10. Wei-Chen Wang, Yuan-Hao Chang, Tei-Wei Kuo, Chien-Chung Ho, Yu-Ming Chang, and Hung-Sheng Chang, "Achieving Lossless Accuracy with Lossy Programming for Efficient Neural-Network Training on NVM-Based Systems," ACM Transactions on Embedded Computing Systems (TECS), vol. 18, no. 5s, pp. 68:1-68:22, Oct. 2019. (Integrated with ACM/IEEE CODES+ISSS'19)
11. Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo, and Ping-Hsien Lin, "Scrubbing-aware Secure Deletion for 3D NAND Flash," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 11, pp. 2790-2801, Nov. 2018. (Integrated with ACM/IEEE CODES+ISSS 2018)
12. Chien-Chung Ho, Yu-Ming Chang, Yuan-Hao Chang, and Tei-Wei Kuo, ”An SLC-Like Programming Scheme for MLC Flash Memory,” ACM Transactions on Storage (TOS), vol. 14, no. 1, pp. 11:1-11:26, Apr. 2018.
13. Chien-Chung Ho, Yu-Ming Chang, Yuan-Hao Chang, Hsiu-Chang Chen, and Tei-Wei Kuo, ”Write-aware memory management for hybrid SLC-MLC PCM memory systems,” ACM SIGAPP Applied Computing Review (ACR), vol. 17, no. 2, pp. 16-26, Aug. 2017.
14. Chien-Chung Ho, Yu-Ping Liu, Yuan-Hao Chang, Tei-Wei Kuo, "Anti-wear Leveling Design for SSDs with Hybrid ECC Capability," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 25, no. 2, pp. 488-501, Feb. 2017.
15. Chien-Chung Ho, Sheng-Wei Cheng, Yuan-Hao Chang, Yu-Ming Chang, Sheng-Yen Hong, and Che-Wei Chang, ”Efficient Hibernation Resuming with Classification-based Prefetching Scheme for Embedded Computing Systems,” ACM SIGAPP Applied Computing Review (ACR), vol. 15, no. 1, pp. 33-43, Mar. 2015.

Conference Papers:

1. Cheng-You Fang, Han-Yu Liao, and Chien-Chung Ho, "Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash," ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, Jan. 25-28, 2027.
2. Guan-Tze Li, Liang-Chi Chen, Chien-Chung Ho, Yu-Ming Chang, and Yuan-Hao Chang, "Bi-Tiered Page Caching Design over CXL-enabled SSDs for Unlocking Fine-Grained I/O Bottleneck," ACM International Conference on Research in Adaptive and Convergent Systems (RACS), Fukuoka, Japan, Nov. 17-20, 2026.
3. Jo-Ling Huang, Liang-Chi Chen, Chien-Chung Ho, and Yuan-Hao Chang, "LAMP: An Adaptive Near-Memory Processing System for High-Performance Long-Read Mapping," ACM/IEEE Design, Automation and Test in Europe (DATE) (Acceptance rate: 24.8% (325/1310)), Verona, Italy, Apr. 20 - 22, 2026. (Top Conference)
4. Hasan Alhasan, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "EPCO: ECC and Processor-Aided Computational Offloading for Efficient In-Storage Video Querying," International Conference on Emerging Technologies and Engineering Systems (ICETES), Amman, Jordan, April 7-9, 2026.
5. Guan-De Jiang, Ying-Sheng Huang, Liang-Chi Chen, and Chien-Chung Ho, "Accelerating RNA-Seq Pseudoalignment via NAND Flash-based In-Memory-Searching Architecture," ACM/SIGAPP Symposium On Applied Computing (SAC), March 23-27, 2026.
6. Liang-Chi Chen, Chien-Chung Ho, Tei-Wei Kuo, and Yuan-Hao Chang, "AridWalk: Efficient Graph Random Walks on a Resource-Limited Computational Storage Device," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Reykjavik, Iceland, Aug. 6-8, 2025. (Top Conference)
7. Chun-Le Yeh, Liang-Chi Chen, Chien-Chung Ho, Yu-Ming Chang, and Da-Wei Chang, "PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System," ACM/IEEE Design Automation Conference (DAC) (Acceptance rate: 22.6% (420/1862)), San Francisco, CA, USA, June 22-25, 2025. (Top Conference)
8. Liang-Chi Chen, Kun-Chi Chiang, Chien-Chung Ho, Yu-Ming Chang, Chin-Chiang Pan, and Yuan-Hao Chang, "LifeSqueezer: Increase the Tolerability of Weak Pages for Lifetime Improvement on TLC-based SSDs with the Off-the-shelf ECC," ACM International Conference on Research in Adaptive and Convergent Systems (RACS), Pompei, Italy, Nov. 5-8, 2024.
9. Lee Chang, Chien-Chung Ho, and Tei-Wei Kuo, "Alleviating Deduplication-oriented Fragmentation of SSDs by Considering File Hotness and Popularity," The 20th IEEE International SoC Conference (ISOCC), Jeju, South Korea, Oct. 25-28, 2023.
10. Shin-Ting Wu, Liang-Chi Chen, Po-Chun Huang, Yuan-Hao Chang, Chien-Chung Ho, and Wei-Kuan Shih, "WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Germany, Sep. 17-22, 2023. (Journal Track, Integrated with ACM TECS) (Top Conference)
11. Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo, and Yu-Ming Chang, "Retention Leveling: Leverage Retention Refreshing and Wear Leveling Techniques to Enhance Flash Reliability with the Awareness of Temperature," IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), TOKI MESSE, Niigata, Japan, August 30 - September 1, 2023.
12. Liang-Chi Chen,  Chien-Chung Ho, and Yuan-Hao Chang, "UpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, July 9-13, 2023. (Top Conference)
13. Liang-Chi Chen, Shu-Qi Yu, Chien-Chung Ho, Wei-Chen Wang, and Yung-Chun Li, "Efficient Sanitization Design for LSM-based Key-Value Store over 3D MLC NAND Flash," ACM/SIGAPP Symposium On Applied Computing (SAC), March 27 - March 31, 2023.
14. Liang-Chi Chen, Shu-Qi Yu, Chien-Chung Ho, Yuan-Hao Chang, Da-Wei Chang, Wei-Chen Wang, Yu-Ming Chang, "RNA-seq Quantification on Processing in Memory Architecture: Observation and Characterization," IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), August 23-25, 2022.
15. Hasan Alhasan, Yun-Chih Chen, Chien-Chung Ho, Tei-Wei Kuo, "RUSM: Harnessing Unused Resources in 3D NAND SSD to Enhance Reading Performance," IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), August 23-25, 2022.
16. Chien-Chung Ho, Wei-Chen Wang, Szu-Yu Chen, Yung-Chun Li, and Kun-Chi Chiang, "RAM: Exploiting Restrained and Approximate Management for Enabling Neural Network Training on NVM-based Systems," ACM/SIGAPP Symposium On Applied Computing (SAC), April 25 - April 29, 2022.
17. Yu-Ming Chang, Chien-Chung Ho, Che-Wei Tsao, Shu-Hsien Liao, Wei-Chen Wang, Tei-Wei Kuo, and Yuan-Hao Chang, "On Enduring More Data Through Enabling Page Rewrite Capability on Multi-level-cell Flash Memory," ACM/SIGAPP Symposium On Applied Computing (SAC), April 25 - April 29, 2022.
18. Chien-Chung Ho, Wei-Chen Wang, Te-Hao Hsu, Zhi-Duan Jiang, and Yung-Chun Li, "Approximate Programming Design for Enhancing Energy, Endurance and Performance of Neural Network Training on NVM-based Systems," IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), August 18-20, 2021. (Best Paper Award)
19. Hasan Alhasan, Yun-Chih Chen, and Chien-Chung Ho, "RVO: Unleashing SSD's Parallelism by Harnessing the Unused Power," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), hybrid Zoom/Boston, MA, USA, Jul. 26-28, 2021. (Top Conference) (Best Paper Nomination)
20. Wei-Chen Wang, Chien-Chung Ho, Yu-Ming Chang, and Yuan-Hao Chang, "Challenges and Designs for Secure Deletion in Storage Systems," IEEE International Conference on Computing, Analytics, and Networks (ICAN), Chiayi, Taiwan, Feb. 7-8, 2020.
21. Wei-Chen Wang, Ping-Hsien Lin, Yung-Chun Li, Chien-Chung Ho, Yu-Ming Chang, and Yuan-Hao Chang, "Toward Instantaneous Sanitization through Disturbance-induced Errors and Recycling Programming over 3D Flash Memory," ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, Nov. 4-7, 2019. (Acceptance rate: 23.8%(94/394)) (Top Conference)
22. Wei-Chen Wang, Yuan-Hao Chang, Tei-Wei Kuo, Chien-Chung Ho, Yu-Ming Chang, and Hung-Sheng Chang, "Achieving Lossless Accuracy with Lossy Programming for Efficient Neural-Network Training on NVM-Based Systems," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA, Oct. 13-18, 2019. (Journal Track, Integrated with ACM TECS)(Top Conference)(Best Paper Award)
23. Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo, and Ping-Hsien Lin, "Scrubbing-aware Secure Deletion for 3D NAND Flash," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Torino, Italy, Sep. 30 - Oct. 5, 2018. (Journal Track, Integrated with IEEE TCAD)(Top Conference)
24. Ping-Hsien Lin, Yu-Ming Chang, Yung-Chun Li, Wei-Chen Wang, Chien-Chung Ho and Yuan-Hao Chang, "Achieving Fast Sanitization with Zero Live Data Copy for MLC Flash Memory," ACM/IEEE International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, Nov. 5-8, 2018.(Top Conference)
25. Chien-Chung Ho, Yung-Chun Li, Ping-Hsien Lin, Wei-Chen Wang and Yuan-Hao Chang. "A Stride-away Programming Scheme to Resolve Crash Recoverability and Data Readability Issues of Multi-level-cell Flash Memory", IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), Hakodate, Japan, August 28-31, 2018.
26. Chien-Chung Ho, Yung-Chun Li, Yuan-Hao Chang, and Yu-Ming Chang, "Achieving Defect-Free Multilevel 3D Flash Memory with One-Shot Program Design", ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 24-28, 2018. (Acceptance rate: 24.3%(168/691))(Top Conference)
27. Chin-Chiang Pan, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo, Yu-Ming Chang, and Ming-Chang Yang, “Boosting the Performance with a Data-backup-free Programming Scheme for TLC-based SSDs,”  ACM/SIGAPP Symposium On Applied Computing (SAC), Pau, France, Apr. 9-13, 2018.
28. Hsin-Yu Chang, Chien-Chung Ho, Yuan-Hao Chang, Yu-Ming Chang, and Tei-Wei Kuo, “How to Enable Software Isolation and Boost System Performance with Sub-block Erase over 3D Flash Memory,” ACM/IEEE International Conference on Computer-Aided Design (CODES+ISSS), Pittsburgh, PA, USA, Oct. 2-7, 2016.(Top Conference)
29. Tseng-Yi Chen, Yuan-Hao Chang, Chien-Chung Ho, and Shuo-Han Chen, ”Enabling Sub-blocks Erase Management to Boost the Performance of 3D NAND Flash Memory,” ACM/IEEE Design Automation Conference (DAC), Austin, Texas, USA, Jun. 5-9, 2016. (Best Paper Nomination (16/674))(Top Conference)
30. Wei-Cheng Wang, Chien-Chung Ho, Che-Wei Tsao, Yuan-Hao Chang, Tse-Yuan Wang, Kun-Cheng Hsu, and Tei-Wei Kuo, ”Data Sanitization for Hard Disk Drives and Solid-State Drives,” Symposium on Digital Life Technologies (DLT), Pingtung, Taiwan, Jun. 18-19, 2016.
31. Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, ”Access Pattern Reshaping for eMMC-enabled SSDs,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Austin, Texas, USA, Nov. 2-6, 2015. (Acceptance rate: 24.7%(94/381))(Top Conference)
32. Che-Wei Tsao, Chun-Yi Liu, Chien-Chung Ho, Tse-Yuan Wang, Po-Chun Huang, Yuan-Hao Chang, and Tei-Wei Kuo, ”Rethinking I/O Request Management over eMMC-based Solid-State Drives,” ACM Research in Adaptive and Convergent Systems (RACS), Prague, Czech Republic, Oct. 9-12, 2015.
33. Chien-Chung Ho, Yuan-Hao Chang, Che-Wei Tsao, and Pei-Lun Suei, ”Block Reinforcement to Optimize Lifetime of Flash Storage Devices,” IEEE Global Conference on Consumer Electronics (GCCE), Tokyo, Japan, Oct. 7-10, 2014.
34. Chien-Chung Ho, Yu-Ming Chang, Yuan-Hao Chang, Sheng-Yen Hong, Che-Wei Chang, and Tei-Wei Kuo, ”A Classification-based Prefetching Scheme for Hibernation of Embedded Computing Systems,” ACM Research in Adaptive and Convergent Systems (RACS), Baltimore, Maryland, USA, Oct. 5-8, 2014.
35. Chien-Chung Ho, Hui-Wen Chen, Yuan-Hao Chang, Yu-Ming Chang, Po-Chun Huang, Tei-Wei Kuo, and David Hung-Chang Du, “Energy-Aware Data Placement Strategy for SSD-Assisted Streaming Video Servers,” IEEE Nonvolatile Memory Systems and Applications Symposium (NVMSA), Chongqing, China, Aug. 20–21, 2014.
36. Tzu-Jung Huang, Chien-Chung Ho, Po-Chun Huang, Yuan-Hao Chang, Che-Wei Chang, and Tei-Wei Kuo, “Current-Aware Scheduling for Flash Storage Devices,” IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Chongqing, China, Aug. 20–22, 2014.
37. Chien-Chung Ho, Po-Chun Huang, Yuan-Hao Chang, and Tei-Wei Kuo, ”A DRAM-Flash Index for Native Flash File Systems,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Montreal, Canada, Sep. 29 - Oct. 4, 2013. (Top Conference)
38. Po-Chun Huang, Yuan-Hao Chang, Tei-Wei Kuo, Chien-Chung Ho, and Hyunseung Choo, ”Joint Management of Performance-predictable Virtualized Storage Devices with Hard Disk and Flash Memory,” ACM Research in Adaptive and Convergent Systems (RACS), Montreal, Canada, Oct. 1-4, 2013.
39. Shuo-Hung Chen, Hsiao-Mei Lin, Kuo-Yi Chen, Yuan-Hao Chang, Pen-Chung Yew, and Chien-Chung Ho, ”A Systematic Methodology for OS Benchmark Characterization,” ACM Research in Adaptive and Convergent Systems (RACS), Montreal, Canada, Oct. 1-4, 2013.

Patents:

• US Patents
  1. Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Operating Method Thereof," US 12,625,676 B2; Issued May 12, 2026.
  2. Wei-Chen Wang, Shu-Yin Ho, Chien-Chung Ho, and Yuan-Hao Chang, "Operation Method for Artificial Neural Network," US 12,327,185 B2; Issued Jun 10, 2025.
  3.  Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "In-Memory Computing Method and Apparatus," US 12,050,888 B2; Issued Jul 30, 2024.
  4.  Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Operating Method Thereof," US 11,966,628 B2; Issued Apr 23, 2024.
  5.  Wei-Chen Wang, Hung-Sheng Chang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Wear Leveling Method for the Same," US 11,550,709 B2; Issued Jan 10, 2023.
  6.  Wei-Chen Wang, Hung-Sheng Chang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device for Neural Networks," US 11,526,285 B2; Issued Dec 13, 2022.
  7.  Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Operating Method Thereof," US 2023/0221956 A1; Published Jul 13, 2023.
  8. Yung-Chun Li, Ping-Hsien Lin, Shu-Yin Ho, Chien-Chung Ho, "Operation method for artificial neural network," U.S. Patent US20210158160A1, May 2021
  9. Yung-Chun Li, Ping-Hsien Lin, Kun-Chi Chiang, Chien-Chung Ho, "Memory data management method," U.S. Patent US11010244B2, May 2021
  10. Yu-Ming Chang, Hsiang-Pang Li, Hsin-Yu CHANG, Chien-Chung Ho, Yuan-Hao Chang, “Erasing method and memory device using the same”, U.S. Patent No. 9,754,637. 5 Sep. 2017
• China Patents
  1.  Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "In-Memory Operation Method and Device," CN 113537453 B; Issued Apr 1, 2025.
  2.  Ping-Hsien Lin, Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo, Yu-Ming Chang, "Memory Device and Data Management Method Applied Thereto," CN 109710173 B; Issued Dec 3, 2021.
  3.  Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Method of Operating the Same" CN 116469427 A; Published Jul 21, 2023.
  4.  Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Method of Operating the Same" CN 116469426 A; Published Jul 21, 2023.
  5. Wei-Chen Wang, Shu-Yin Ho, Chien-Chung Ho, Yuan-Hao Chang, “Operation Method of Neural Network,” CN 112948753 A; Issued Jun 11, 2021.
• Taiwan Patents
  1.  Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Operating Method Thereof," TW I806641 B; Issued Jun 21, 2023.
  2.  Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, and Tei-Wei Kuo, "Memory Device and Operating Method Thereof," TW I806640 B; Issued Jun 21, 2023.
  3.  Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo, "In-Memory Computing Method and In-Memory Computing Apparatus," TW I792247 B; Issued Feb 11, 2023.
  4.  Wei-Chen Wang, Yung-Chun Li, Shu-Yin Ho, Chien-Chung Ho, "Memory Device and Memory Operation Method," TW I780967 B; Issued Oct 11, 2022.
  5.  Wei-Chen Wang, Shu-Yin Ho, Chien-Chung Ho, Yuan-Hao Chang, "Operation Method for Artificial Neural Network," TW I770668 B; Issued Jul 11, 2022.
  6.  Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, "Neural Network System and Memory Operation Method," TW 202230220 A; Published Aug 1, 2022.
  7.  Ping-Hsien Lin, Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo, Yu-Ming Chang, "Memory Device and Data Management Method Thereof," TW I629592 B; Issued Jul 11, 2018.

Special Column:

1. Chien-Chung Ho, “What is Incremental Step Pulse Programming (ISPP)?”, SIGDA NEWSLETTER, 1 May 2018, Vol. 48, No. 5  

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